foxPSL: A Fast, Optimized and eXtended PSL implementation

نویسندگان

  • Sara Magliacane
  • Philip Stutz
  • Paul T. Groth
  • Abraham Bernstein
چکیده

Article history: Received 16 December 2014 Received in revised form 15 April 2015 Accepted 28 May 2015 Available online 5 June 2015

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Property - based Synthesis of Optimized Büchi Automata ( Deliverable

Dissemination Level PU Public ⊠ PP Restricted to other programme participants (including the Commission Services) RE Restricted to a group specified by the consortium (including the Commission Services) CO Confidential, only for members of the consortium (including the Commission Services) Notices For information, contact Roderick Bloem [email protected]. This document is intended to fulfil ...

متن کامل

PSL Assertion Checking with Temporally Extended High-Level Decision Diagrams

The paper proposes a novel method for PSL language assertions conversion to a system representation model called High-Level Decision Diagrams (HLDD). Previous works have shown that HLDDs are an efficient model for simulation and convenient for diagnosis and debug. We present a technique, where checking of PSL assertions is integrated into fast HLDDbased simulation. There are three main contribu...

متن کامل

Neun Portable Standard LISP for Cray X - MP Computers Preprint SC 86 - 2 ( Dezember 1986 )

Portable Standard LISP (PSL) is a portable implementation of the programming language LISP constructed at the University of Utah. The version 3.4 of PSL was implemented for Cray X-MP computers by KonradZuse-Zentrum Berlin; this implementation is based to an important part on the earlier implementation of PSL 3.2 at the University of Utah, Los Alamos National Laboratories and Cray Research Inc. ...

متن کامل

Low-Power Adder Design for Nano-Scale CMOS

A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.

متن کامل

Nonlinear optimized Fast Locking PLLs Using Genetic Algorithm

Abstract— This paper presents a novel approach to obtain fast locking PLL by embedding a nonlinear element in the loop of PLL. The nonlinear element has a general parametric Taylor expansion. Using genetic algorithm (GA) we try to optimize the nonlinear element parameters. Embedding optimized nonlinear element in the loop shows enhancements in speed and stability of PLL. To evaluate the perform...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:
  • Int. J. Approx. Reasoning

دوره 67  شماره 

صفحات  -

تاریخ انتشار 2015